MEC1322 datasheet(297/456 Pages) MICROCHIP

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DS00001719D-page 297

MEC1322

26.9.1

FAN SETTING REGISTER

The Fan Setting Registers are used to control the output of the Fan Driver. The driver setting operates independently

of the Polarity bit for the PWM output. That is, a setting of 00h will mean that the fan drive is at minimum drive while a

value of FFh will mean that the fan drive is at maximum drive.

If the Spin Up Routine is invoked, reading from the registers will return the current fan drive setting that is being used

by the Spin Up Routine instead of what was previously written into these registers.

The Fan Driver Setting Registers, when the RPM based Fan Control Algorithm is enabled, are read only. Writing to the

register will have no effect and the data will not be stored. Reading from the register will always return the current fan

drive setting.

If the INT_PWRGD pin is de-asserted, the Fan Driver Setting Register will be made read only. Writing to the register will

have no effect and reading from the register will return 000h.

When the RPM based Fan Control Algorithm is disabled, the current fan drive setting that was last used by the algorithm

is retained and will be used.

If the Fan Driver Setting Register is set to a value of 00h, all tachometer related status bits will be masked until the setting

is changed. Likewise, the FAN_SHORT bit will be cleared and masked until the setting is changed.

The contents of the register represent the weighting of each bit in determining the final duty cycle. The output drive for

a PWM output is given by the following equation:

- Drive = (FAN_SETTING VALUE/255) x 100%.

26.9.2

PWM DIVIDE REGISTER

The PWM Divide Register determines the final PWM frequency. The base frequency set by the PWM_BASE[1:0] bits is

divided by the decimal equivalent of the register settings.

The final PWM frequency is derived as the base frequency divided by the value of this register as shown in the equation

below:

- PWM_Frequency = base_clk / PWM_D

Where:

- base_clk = The base frequency set by the PWMx_CFG[1:0] bits

- PWM_D = the divide setting set by the PWM Divide Register.

Tach Reading High Byte

0Fh

PWM Driver Base Frequency

10h

Fan Status

11h

Offset

00h

Bits

Description

Type

Default

Reset

Event

7:0 FAN_SETTING[7:0]

The Fan Driver Setting used to control the output of the Fan Driver.

R/W

00h

VCC1_R

ESET

Offset

01h

Bits

Description

Type

Default

Reset

Event

7:0 PWM_DIVIDE[7:0]

The PWM Divide value determines the final frequency of the PWM

driver. The driver base frequency is divided by the PWM Divide

value to determine the final frequency.

R/W

01h

VCC1_R

ESET

TABLE 26-8:

FAN CONTROL REGISTER SUMMARY (CONTINUED)

Offset

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