DLPC910 datasheet(14/50 Pages) TI1

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DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

www.ti.com

6.4 Thermal Information

DLPC910

THERMAL METRIC (1)

ZYR (FCBGA)

UNIT

676 PINS

RθJA

Junction-to-ambient thermal resistance (2)

12.1

°C/W

RθJC

Junction-to-case thermal resistance

3.2

°C/W

RθJB

Junction-to-board thermal resistance

0.19

°C/W

(1)

Refer to the XC5VLX30 product specifications at www.xilinx.com for complete thermal specifications.

(2)

In still air.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

VIH

High-level input voltage

3.3-V CMOS

2.0

VIL

Low-level input voltage

3.3-V CMOS

0.8

VOH

High-level output voltage

3.3-V DCI and CMOS

2.9

VOL

Low-level output voltage

3.3-V DCI and CMOS

0.4

VIH

High-level input voltage

2.5-V CMOS

1.7

VIL

Low-level input voltage

2.5-V CMOS

0.7

VCCO –

2.5-V interface

0.4

VOH

High-level output voltage

2.5-V LVDS

1.38

2.5-V interface

0.4

VOL

Low-level output voltage

2.5-V LVDS

1.03

2.5-V interface

Input capacitance

2.5-V LVDS

ICCINT

Supply voltage range, core supply

1.4

ICCO

Supply voltage range, I/O supply

4.2

6.6 Timing Requirements

(see

(1))

MIN

NOM

MAX

UNIT

fcd

Clock frequency, DCLKIN_n (2)

fcd = 400 MHz

400

MHz

fcd = 480 MHz

480

fcr

Clock frequency, CLK_R

MHz

Cycle time, DCLKIN_n

fcd = 400 MHz

2.5

fcd = 480 MHz

2.083

tw(H)

Pulse duration, high

50% to 50% reference

fcd = 400 MHz

1.25

points (signal)

fcd = 480 MHz

1.042

tw(L)

Pulse duration, low

50% to 50% reference

fcd = 400 MHz

1.25

points (signal)

fcd = 480 MHz

1.042

Transition time, tt = tf /tr

20% to 80% reference

fcd = 400 MHz

0.6

points (signal)

fcd = 480 MHz

0.5

tjp

Period Jitter DCLKIN_n (3)

100

(1)

It is recommended that the COMP_DATA, NS_FLIP and RST2BLKZ flags be set to one value and not adjusted during normal system

operation.

(2)

Preferred DDC_DCLK _n duty cycle = 50%

(3)

This is the deviation in period from ideal period due solely to high frequency jitter.

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