DLPC910 datasheet(17/50 Pages) TI1

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System Data

Training Data

(0100)

INIT_ACTIVE

4:1 Serdes

Din 3:0

Dout

Sys Clk

IO Clk

DLPC910

www.ti.com

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

Feature Description (continued)

7.3.3 Data Valid

The data valid interface consists of four differential pairs: DVALID_A, DVALID _B, DVALID _C, and DVALID _D.

The DVALID signal should be asserted synchronous to the data it is meant to frame. DVALID can be asserted

as:

•

Framing individual row loads with breaks between rows, or

•

Framing block loads - for example, the DLP9000XFLS with 16 blocks allows framing 100 contiguous row

loads, or

•

Framing the entire DMD load where the DVALID stays active for all DMD row loads with zero invalid data

between rows.

If the DVALID frames DMD blocks or the entire DMD, assure that the block and row control signals are adjusted

at the proper locations in the data stream. Refer to Block Mode Operation for further information.

7.3.4 Interface Training

The DLPC910 detects the phase differences between the ½ speed clock (used in the device driving the LVDS

data) and the internally generated ½ speed data clocks to select a clock phase for data capture. This is done by

supplying a simple repeating pattern on all of the data inputs while the INIT_ACTIVE output of the DLPC910 is

high/active. The details of the training pattern are described below.

Figure 3 shows a simple block diagram of the training pattern insertion logic.

Figure 3. Block Diagram of Training Pattern Logic

The expected training pattern is 0100. In Figure 4, the data input to the 4:1 SERDES cells is captured on the

rising edge of the ½ speed system clock. The output latency shown is based on the documentation for the Xilinx

SERDES cells. Individual implementation may vary depending on the type of cells, technology, and design

technique used.

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