DLPC910 datasheet(38/50 Pages) TI1

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Pixel Data Rate

Min Exposure Period

DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

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Typical Application (continued)

Prior to activating the DVALID signals to the DLPC910, the ROWMD, ROWAD, BLKMD, BLKAD, and

RST2BLKZ control input signals must be in the desired state for the desired operation to take effect on the

DLP9000X DMD. Once the control signals are set, the Apps FPGA activates DVALID and starts loading data

using the DDC_DIN and DDC_DCLK buses. After all data is loaded for the desired DMD operation, the DVALID

signal is de-asserted, and the BLKMD, BLKAD, and RST2BLKZ control signals are set prior to the assertion of

the next DVALID. When DVALID is activated, the MCP causes the prior data to take effect on the mirrors of the

DMD. The Apps FPGA should then monitor the RST_ACTIVE pin to determine when the mirror clock pulse has

completed in order to perform the next MCP. During the time that the RST_ACTIVE is asserted, the Apps FPGA

could be loading data into DMD rows that do not belong to the same block of rows that currently has an

outstanding MCP.

8.2.1.3 Application Curves

In this particular application, the performance plot shown in Figure 15 shows the maximum loaded and displayed

pixels per second when the exposure period is set to its minimum for the different reset modes. When the

exposure period is increased, the pixels per second will decrease. Refer to Mirror Clocking Pulse for more

information regarding exposure period.

Figure 15. Performance Plot at 480 MHz DDC_DCLK

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