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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DLPC910 датащи(PDF) 11 Page - Texas Instruments |
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DLPC910 датащи(HTML) 11 Page - Texas Instruments |
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11 / 50 page  DLPC910 www.ti.com DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015 Pin Functions (continued) PIN ACTIVE I/O TYPE CLOCK SYSTEM DESCRIPTION (HI OR LO) NAME NO. No connect. For access to test point TST_PT_4 AA14 LVCMOS33_O - - output route to test via. No connect. For access to test point TST_PT_5 AB14 LVCMOS33_O - - output route to test via. No connect. For access to test point TST_PT_6 AA15 LVCMOS33_O - - output route to test via. No connect. For access to test point TST_PT_7 AB15 LVCMOS33_O - - output route to test via. No connect. For access to test point TST_PT_8 C1 LVCMOS25_O - - output route to test via. No connect. For access to test point TST_PT_9 D1 LVCMOS25_O - - output route to test via. No connect. For access to test point TST_PT_10 E1 LVCMOS25_O - - output route to test via. No connect. For access to test point TST_PT_11 E2 LVCMOS25_O - - output route to test via. No connect. For access to test point TST_PT_12 E3 LVCMOS25_O - - output route to test via. No connect. For access to test point TST_PT_13 F3 LVCMOS25_O - - output route to test via. No connect. For access to test point TST_PT_14 E7 LVCMOS25_O - - output route to test via. No connect. For access to test point TST_PT_15 F7 LVCMOS25_O - - output route to test via. Requires an external 49.9- Ω pull-up DLPC_VRN_BANK4 AB12 DCI Reference Voltage - - resistor to 3.3 V. Requires an external 49.9- Ω pull- DLPC_VRP_BANK4 AC11 DCI Reference Voltage - - down resistor to GND. Signal enables the Load-4 functionality LOAD4_ENZ D25 LVCMOS33_I Lo - of the DLP9000XFLS. Includes internal pull-up. Signal indicates a DMD voltage is DMD_IRQ D26 LVCMOS33_O Hi - inactive. Includes internal pull-up DLPC910 VBATT reference. Connect to DLPC_VBATT K18 LVCMOS33_I - - GND. DLPC910 Initialization configuration DLPC_DONE K10 LVCOMS33_O - - complete. Connect to DLPR910 CEZ pin. Requires 4.7-k Ω pull-up to 3.3 V. DLPC910 Configuration. Requires 4.7- DLPC_HSWAPEN L18 LVCMOS33_I - - k Ω pull-up to 3.3 V. DLPC910 Configuration. Connect to DDC_M0 W18 LVCMOS33_I - - GND DLPC910 Configuration. Connect to DDC_M1 Y17 LVCMOS33_I - - GND DLPC910 Configuration. Connect to DDC_M2 V18 LVCMOS33_I - - GND DLPC910 Configuration. Connect to INTB_DDC J11 LVCMOS25_O Hi - DLPR910 OE/RESET. Requires 4.7-k Ω pull-up to 3.3 V. DLPC910 Configuration. Connect to PROGB_DDC J18 LVCMOS25_O Hi - DLPR910 CF. Requires 4.7-k Ω pull-up to 3.3 V. Configuration PROM Clock. Connect to DLPR910 CLK. Connects to center of PROM_CCK_DDC J10 LVCMOS25_O - PROM_CCK_DDC voltage divider (100/100- Ω 3.3 V and GND). Configuration PROM Data in. PROM_D0_DDC K11 LVCMOS25_I - PROM_CCK_DDC Connected to DLPR910 Data 0 (D0) DLPC910 Configuration. Requires 1-k Ω RDWR_B P18 LVCMOS25_I - - pull-down to ground. JTAG Clock. Connects to DLPC910, DLPR910, and JTAG header TCK (if TCK_JTAG U11 LVCMOS33_I - TCK_JTAG user has JTAG they must build their chain accordingly) JTAG Data out of DLPC910. Connects TDO_DDC W10 LVCMOS33_O - TCK_JTAG to JTAG return TDO on JTAG header JTAG Data out of DLPR910 to TDO_XCF16DDC V11 LVCMOS33_I - TCK_JTAG DLPC910. Connects to DLPR910 TDO (DLPC910 internal signal TDI_0) Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DLPC910 |
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