DLPC910 datasheet(28/50 Pages) TI1

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Load Block 14

Load Block 15

DIN_A/B/C/D

Reset Block 14

Reset Block 15

BLK_MD/BLK_AD

RST_ACTIVE

Load Block 0

Block 13

Reset Block 13

Block 12

Reset Block 0

Load Block 1

Exposure Period

Mirror

Settling Time

for Block 15

DCLKIN

DVALID

ROWMD

BLK_MD

BLK_AD

XXXX

DLPC910

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

www.ti.com

NOTE

While RST_ACTIVE is high for 4

μs, the data for the block(s) being issued a MCP should

not be changed to allow the mirrors to become stable. The RST_ACTIVE does not include

the mirror settling period. A short delay of 6

μs should be introduced during the last

block(s) that is issued a MCP. The mirror settling time is illustrated in Figure 10, Figure 11,

Figure 12, and Figure 13, where the customer interface introduces a delay on the last

block(s) that were issued a MCP to allow the mirrors to become stable.

Figure 10, Figure 11, Figure 12, and Figure 13 all show an exposure period. Once the customer interface has

issued all required MCPs and the proper mirror settling time has been applied, the customer interface may pulse

an illumination source onto the DMD during this period. The exposure period is user adjustable; however,

increasing the exposure period decreases the pattern rate. Refer to Application Curves regarding exposure

period.

Figure 9. DMD No-op Row Cycle

Figure 10. Single Block Load Phased Sequence

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