UPSD3312D datasheet(37/272 Pages) STMICROELECTRONICS

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UPSD33xx

8032 MCU registers

Doc ID 9685 Rev 7

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8032 MCU registers

The UPSD33xx has the following 8032 MCU core registers, also shown in Figure 10.

Figure 10.

8032 MCU registers

7.1

Stack Pointer (SP)

The SP is an 8-bit register which holds the current location of the top of the stack. It is

incremented before a value is pushed onto the stack, and decremented after a value is

popped off the stack. The SP is initialized to 07h after reset. This causes the stack to begin

at location 08h (top of stack). To avoid overlapping conflicts, the user must initialize the top

of the stack to 20h if all four banks of registers R0 - R7 are used, and the user must initialize

the top of stack to 30h if all of the 8032 bit memory locations are used.

7.2

Data Pointer (DPTR)

DPTR is a 16-bit register consisting of two 8-bit registers, DPL and DPH. The DPTR register

is used as a base register to create an address for indirect jumps, table look-up operations,

and for external data transfers (XDATA). When not used for addressing, the DPTR register

can be used as a general purpose 16-bit data register.

Very frequently, the DPTR register is used to access XDATA using the External Direct

addressing mode. The UPSD33xx has a special set of SFR registers (DPTC, DPTM) to

control a secondary DPTR register to speed memory-to-memory XDATA transfers. Having

dual DPTR registers allows rapid switching between source and destination addresses (see

details in Section 11: Dual data pointers on page 56).

7.3

Program Counter (PC)

The PC is a 16-bit register consisting of two 8-bit registers, PCL and PCH. This counter

indicates the address of the next instruction in program memory to be fetched and executed.

A reset forces the PC to location 0000h, which is where the reset jump vector is stored.

AI06636

Accumulator

B Register

Stack Pointer

Program Counter

Program Status Word

General Purpose

Data Pointer Register

PCH

DPTR(DPH)

PCL

PSW

R0-R7

DPTR(DPL)

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