UPSD3312D datasheet(97/272 Pages) STMICROELECTRONICS

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UPSD33xx

Standard 8032 timer/counters

Doc ID 9685 Rev 7

97/272

20.5.4

Mode 3

Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1 = 0.

Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters. The logic for mode 3

on Timer 0 is shown in Figure 23 on page 99. TL0 uses the Timer 0 control Bits: C/T, GATE,

TR0, and TF0, as well as the pin EXTINT0. TH0 is locked into a timer function (counting at a

rate of 1/12 fOSC) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now

controls the “Timer 1“ interrupt flag.

Mode 3 is provided for applications requiring an extra 8-bit timer on the counter (see

Figure 23 on page 99). With Timer 0 in mode 3, a UPSD33xx device can look like it has

three Timer/Counters (not including the PCA). When Timer 0 is in mode 3, Timer 1 can be

turned on and off by switching it out of and into its own mode 3, or can still be used by the

serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.

Table 56.

TMOD: Timer Mode register (SFR 89h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GATE

C/T

M[1:0]

GATE

C/T

M[1:0]

Table 57.

TMOD register bit definition

Bit

Symbol

R/W

Timer

Definition (T/C is abbreviation for

timer/counter)

7GATE

R,W

Timer 1

Gate control.

When GATE = 1, T/C is enabled only while pin

EXTINT1 is '1' and the flag TR1 is '1.' When GATE

= 0, T/C is enabled whenever the flag TR1 is '1.'

6C/T

R,W

Counter or Timer function select.

When C/T = 0, function is timer, clocked by

internal clock. C/T = 1, function is counter, clocked

by signal sampled on external pin, C1.

[5:4]

M[1:0]

R,W

Mode Select.

00b = 13-bit T/C. 8 bits in TH1 with TL1 as 5-bit

pre-scaler.

01b = 16-bit T/C. TH1 and TL1 are cascaded. No

pre-scaler.

10b = 8-bit auto-reload T/C. TH1 holds a constant

and loads into TL1 upon overflow.

11b = Timer Counter 1 is stopped.

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