UPSD3312D datasheet(59/272 Pages) STMICROELECTRONICS

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UPSD33xx

Debug unit

Doc ID 9685 Rev 7

59/272

Debug unit

The 8032 MCU module supports run-time debugging through the JTAG interface. This same

JTAG interface is also used for in-system programming (ISP) and the physical connections

are described in the PSD module section, Section 27.5.1: JTAG ISP and JTAG debug on

page 233.

Debugging with a serial interface such as JTAG is a non-intrusive way to gain access to the

internal state of the 8032 MCU core and various memories. A traditional external hardware

emulator cannot be completely effective on the UPSD33xx because of the Pre-Fetch Queue

and Branch Cache. The nature of the PFQ and BC hide the visibility of actual program flow

through traditional external bus connections, thus requiring on-chip serial debugging

instead.

Debugging is supported by Windows PC based software tools used for 8051 code

development from 3rd party vendors listed at www.st.com/mcu. Debug capabilities include:

●

Halt or start MCU execution

●

Reset the MCU

●

Single step

●

3 match breakpoints

●

1 range breakpoint (inside or outside range)

●

Program tracing

●

Read or modify MCU core registers, DATA, IDATA, SFR, XDATA, and code

●

External Debug Event pin, input or output

Some key points regarding use of the JTAG debugger.

●

The JTAG debugger can access MCU registers, data memory, and code memory while

the MCU is executing at full speed by cycle-stealing. This means “watch windows” may

be displayed and periodically updated on the PC during full speed operation. registers

and data content may also be modified during full speed operation.

●

There is no on-chip storage for Program Trace data, but instead this data is scanned

from the UPSD33xx through the JTAG channel at run-time to the PC host for

processing. As such, full speed program tracing is possible only when the 8032 MCU is

operating below approximately one MIPS of performance. Above one MIPS, the

program will not run real-time while tracing. One MIPS performance is determined by

the combination of choice for MCU clock frequency, and the bit settings in SFR

registers BUSCON and CCON0.

●

Breakpoints can optionally halt the MCU, and/or assert the external Debug Event pin.

●

Breakpoint definitions may be qualified with read or write operations, and may also be

qualified with an address of code, SFR, DATA, IDATA, or XDATA memories.

●

Three breakpoints will compare an address, but the fourth breakpoint can compare an

address and also data content. Additionally, the fourth breakpoint can be logically

combined (AND/OR) with any of the other three breakpoints.

●

The Debug Event pin can be configured by the PC host to generate an output pulse for

external triggering when a break condition is met. The pin can also be configured as an

event input to the breakpoint logic, causing a break on the falling-edge of an external

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