UPSD3312D datasheet(33/272 Pages) STMICROELECTRONICS

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UPSD33xx

8032 MCU core performance enhancements

Doc ID 9685 Rev 7

33/272

Figure 7.

Instruction pre-fetch queue and branch cache

5.1

Pre-Fetch Queue (PFQ) and Branch Cache (BC)

The PFQ is always working to minimize the idle bus time inherent to 8032 MCU architecture,

to eliminate wasted memory fetches, and to maximize memory bandwidth to the MCU. The

PFQ does this by running asynchronously in relation to the MCU, looking ahead to pre-fetch

code from program memory during any idle bus periods. Only necessary bytes will be

fetched (no dummy fetches like standard 8032). The PFQ will queue up to six code bytes in

advance of execution, which significantly optimizes sequential program performance.

However, when program execution becomes non-sequential (program branch), a typical pre-

fetch queue will empty itself and reload new code, causing the MCU to stall. The Turbo

UPSD33xx diminishes this problem by using a Branch Cache with the PFQ. The BC is a

four-way, fully associative cache, meaning that when a program branch occurs, it's branch

destination address is compared simultaneously with four recent previous branch

destinations stored in the BC. Each of the four cache entries contain up to six bytes of code

related to a branch. If there is a hit (a match), then all six code bytes of the matching

program branch are transferred immediately and simultaneously from the BC to the PFQ,

and execution on that branch continues with minimal delay. This greatly reduces the chance

that the MCU will stall from an empty PFQ, and improves performance in embedded control

systems where it is quite common to branch and loop in relatively small code localities.

By default, the PFQ and BC are enabled after power-up or reset. The 8032 can disable the

PFQ and BC at runtime if desired by writing to a specific SFR (BUSCON).

The memory in the PSD module operates with variable wait states depending on the value

specified in the SFR named BUSCON. For example, a 5 V UPSD33xx device operating at a

40 MHz crystal frequency requires four memory wait states (equal to four MCU clocks). In

this example, once the PFQ has one or more bytes of code, the wait states become

Branch 4

Code

Branch 4

Code

Branch 4

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Branch 4

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Branch 4

8032

MCU

Program

Memory on

PSD Module

Instruction Pre-Fetch Queue (PFQ)

6 Bytes of Instruction

Instruction

Byte

Wait

Stall

Instruction

Byte

Current

Branch

Address

Compare

Branch

Cache

(BC)

AI08809

Address

Load on Branch Address Match

Branch 3

Code

Branch 3

Code

Branch 3

Code

Branch 3

Code

Branch 3

Code

Branch 3

Code

Branch 3

Branch 2

Code

Branch 2

Code

Branch 2

Code

Branch 2

Code

Branch 2

Code

Branch 2

Code

Branch 2

Branch 1

Code

Branch 1

Code

Branch 1

Code

Branch 1

Code

Branch 1

Code

Branch 1

Code

Branch 1

Address

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