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UPSD3312D датащи(PDF) 69 Page - STMicroelectronics

номер детали UPSD3312D
подробное описание детали  fast 8032 MCU with programmable logic
PDF  272 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3312D датащи(HTML) 69 Page - STMicroelectronics

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UPSD33xx
MCU clock generation
Doc ID 9685 Rev 7
69/272
Figure 13.
Clock generation logic
Table 28.
CCON0 register bit definition
XTAL1 /2
XTAL1 /4
XTAL1 /2048
Q
Q
Q
M
U
X
XTAL1 (default)
XTAL1 /8
XTAL1 /16
Q
Q
XTAL1 /32
XTAL1 /1024
Q
Q
0
1
2
3
4
5
6
7
XTAL1
(fOSC)
PCON[1]: PD,
Power-Down Mode
CCON[2:0]
Clock Pre-Scaler Select
PCON[0]: IDL,
Idle Mode
Clock Divider
MCU_CLK (fMCU)
(to: 8032, WDT)
PERIPH_CLK (fOSC)
(to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC)
3
AI09197b
Table 27.
CCON0: Clock Control register (SFR F9h, reset value 10h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
DBGCE
CPUAR
CPUPS[2:0]
Bit
Symbol
R/W
Definition
7–
–
Reserved
6–
–
Reserved
5–
–
Reserved
4
DBGCE
R,W
Debug Unit Breakpoint Comparator Enable
0 = JTAG debug unit comparators are disabled
1 = JTAG debug unit comparators are enabled (Default condition after reset)
3
CPUAR
R,W
Automatic MCU Clock Recovery
0 = There is no change of CPUPS[2:0] when an interrupt occurs.
1 = Contents of CPUPS[2:0] automatically become 000b whenever any
interrupt occurs.
2:0
CPUPS
R,W
MCUCLK Pre-Scaler
000b: fMCU = fOSC (Default after reset)
001b: fMCU = fOSC/2
010b: fMCU = fOSC/4
011b: fMCU = fOSC/8
100b: fMCU = fOSC/16
101b: fMCU = fOSC/32
110b: fMCU = fOSC/1024
111b: fMCU = fOSC/2048



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