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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 30 of 62
CY37192V
CY37256V
Typical 3.3V Power Consumption (continued)
0
20
40
60
80
100
120
0
2 0
4 0
6 0
8 0
100
120
Fr e q ue n c y ( M H z )
Lo w P o w e r
H ig h S p eed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
0
20
40
60
80
100
120
140
0
2 0
4 0
6 0
8 0
100
120
Fr e q ue n c y ( M H z )
Low P o w e r
H ig h S p eed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
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