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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 27 of 62
CY37256
CY37384
Typical 5.0V Power Consumption (continued)
0
50
100
150
200
250
300
0
2 0
4 0
6 0
8 0
100
120
140
160
180
Fre q ue n c y (M Hz )
Lo w P o w e r
H ig h S peed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
0
50
10 0
15 0
20 0
25 0
30 0
35 0
40 0
45 0
50 0
0
2 04 06 08 0
1 0 0
1 2 0
1 4 0
1 6 0
Fre q ue nc y (M H z)
Low P o w e r
H igh S peed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
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