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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 25 of 62
Power Consumption
Typical 5.0V Power Consumption
CY37032
CY37064
0
10
20
30
40
50
60
0
5 0
100
150
200
250
F re que nc y (M Hz )
H igh S pee d
L o w P o we r
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
0
10
20
30
40
50
60
70
80
90
0
2 0
4 0
6 0
8 0
1 0 0
120
14 0
160
1 8 0
Fre q u e nc y (M H z )
Low P o w e r
H ig h S peed
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