ATmega16 datasheet(174/315 Pages) ATMEL

174 / 315 page

174

ATmega16(L)

2466E–AVR–10/02

TWI register description

TWI Bit Rate Register – TWBR

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a

frequency divider which generates the SCL clock frequency in the Master modes. See

“Bit Rate Generator Unit” on page 172 for calculating bit rates.

TWI Control Register – TWCR

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to

initiate a master access by applying a START condition to the bus, to generate a

receiver acknowledge, to generate a stop condition, and to control halting of the bus

while the data to be written to the bus are written to the TWDR. It also indicates a write

collision if data is attempted written to TWDR while the register is inaccessible.

• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects appli-

cation software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will

jump to the TWI Interrupt Vector. While the TWINT flag is set, the SCL low period is

stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note

that this flag is not automatically cleared by hardware when executing the interrupt rou-

tine. Also note that clearing this flag starts the operation of the TWI, so all accesses to

the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Regis-

ter (TWDR) must be complete before clearing this flag.

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is writ-

ten to one, the ACK pulse is generated on the TWI bus if the following conditions are

met:

The device’s own slave address has been received.

A general call has been received, while the TWGCE bit in the TWAR is set.

A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-

wire Serial Bus temporarily. Address recognition can then be resumed by writing the

TWEA bit to one again.

• Bit 5 – TWSTA: TWI START Condition Bit

The application writes the TWSTA bit to one when it desires to become a master on the

Two-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a

START condition on the bus if it is free. However, if the bus is not free, the TWI waits

Bit

765

432

TWBR7

TWBR6

TWBR5

TWBR4

TWBR3

TWBR2

TWBR1

TWBR0

TWBR

Read/Write

R/W

Initial Value

Bit

765

432

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

TWCR

Read/Write

R/W

Initial Value

ATMEGA16 датащи(PDF) 174 Page - ATMEL Corporation

ATMEGA16 датащи(HTML) 174 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL