ATmega16 datasheet(172/315 Pages) ATMEL

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172

ATmega16(L)

2466E–AVR–10/02

Overview of the TWI

Module

The TWI module is comprised of several submodules, as shown in Figure 84. All regis-

ters drawn in a thick line are accessible through the AVR data bus.

Figure 84. Overview of the TWI Module

SCL and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers

contain a slew-rate limiter in order to conform to the TWI specification. The input stages

contain a spike suppression unit removing spikes shorter than 50 ns. Note that the inter-

nal pullups in the AVR pads can be enabled by setting the PORT bits corresponding to

the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in

some systems eliminate the need for external ones.

Bit Rate Generator Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period

is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in

the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres-

caler settings, but the CPU clock frequency in the slave must be at least 16 times higher

than the SCL frequency. Note that slaves may prolong the SCL low period, thereby

reducing the average TWI bus clock period. The SCL frequency is generated according

to the following equation:

•

TWBR = Value of the TWI Bit Rate Register

•

TWPS = Value of the prescaler bits in the TWI Status Register

Note:

TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than

10, the master may produce an incorrect output on SDA and SCL for the reminder of the

byte. The problem occurs when operating the TWI in Master mode, sending Start + SLA

+ R/W to a slave (a slave does not need to be connected to the bus for the condition to

happen).

TWI Unit

Address Register

(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register

(TWCR)

Status Register

(TWSR)

State Machine and

Status control

SCL

Slew-rate

Control

Spike

Filter

SDA

Slew-rate

Control

Spike

Filter

Bit Rate Generator

Bit Rate Register

(TWBR)

Prescaler

Bus Interface Unit

START / STOP

Control

Arbitration detection

Ack

Spike Suppression

Address/Data Shift

SCL frequency

CPU Clock frequency

2(TWBR) 4

TW PS

⋅

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