ATmega16 datasheet(66/315 Pages) ATMEL

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ATmega16(L)

2466E–AVR–10/02

ISC10) in the MCU General Control Register (MCUCR) define whether the External

Interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity

on the pin will cause an interrupt request even if INT1 is configured as an output. The

corresponding interrupt of External Interrupt Request 1 is executed from the INT1 inter-

rupt Vector.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) in the MCU General Control Register (MCUCR) define whether the External

Interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity

on the pin will cause an interrupt request even if INT0 is configured as an output. The

corresponding interrupt of External Interrupt Request 0 is executed from the INT0 inter-

rupt vector.

• Bit 5 – INT2: External Interrupt Request 2 Enable

When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control2 bit (ISC2) in the MCU

Control and Status Register (MCUCSR) defines whether the External Interrupt is acti-

vated on rising or falling edge of the INT2 pin. Activity on the pin will cause an interrupt

request even if INT2 is configured as an output. The corresponding interrupt of External

Interrupt Request 2 is executed from the INT2 Interrupt Vector.

General Interrupt Flag

• Bit 7 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1

becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU

will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt

routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This flag is always cleared when INT1 is configured as a level interrupt.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0

becomes set (one). If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU

will jump to the corresponding interrupt vector. The flag is cleared when the interrupt

routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This flag is always cleared when INT0 is configured as a level interrupt.

• Bit 5 – INTF2: External Interrupt Flag 2

When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one).

If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. Note that when enter-

ing some sleep modes with the INT2 interrupt disabled, the input buffer on this pin will

be disabled. This may cause a logic change in internal signals which will set the INTF2

flag. See “Digital Input Enable and Sleep Modes” on page 51 for more information.

Bit

76543

210

INTF1

INTF0

INTF2

–

GIFR

Read/Write

R/W

Initial Value

00000

000

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