ATmega16 datasheet(175/315 Pages) ATMEL

175 / 315 page

175

ATmega16(L)

2466E–AVR–10/02

until a STOP condition is detected, and then generates a new START condition to claim

the bus Master status. TWSTA is cleared by the TWI hardware when the START condi-

tion has been transmitted.

• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the

Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit

is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover

from an error condition. This will not generate a STOP condition, but the TWI returns to

a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high

impedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when

TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enable Bit

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is

written to one, the TWI takes control over the I/O pins connected to the SCL and SDA

pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI

is switched off and all TWI transmissions are terminated, regardless of any ongoing

operation.

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit and will always read as zero.

• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will

be activated for as long as the TWINT flag is high.

TWI Status Register – TWSR

• Bits 7..3 – TWS: TWI Status

These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The dif-

ferent status codes are described later in this section. Note that the value read from

TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application

designer should mask the prescaler bits to zero when checking the Status bits. This

makes status checking independent of prescaler setting. This approach is used in this

datasheet, unless otherwise noted.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read as zero.

Bit

765

432

TWS7

TWS6

TWS5

TWS4

TWS3

–

TWPS1

TWPS0

TWSR

Read/Write

R/W

Initial Value

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