ATmega16 datasheet(170/315 Pages) ATMEL

170 / 315 page

170

ATmega16(L)

2466E–AVR–10/02

•

Different masters may use different SCL frequencies. A scheme must be devised to

synchronize the serial clocks from all masters, in order to let the transmission

proceed in a lockstep fashion. This will facilitate the arbitration process.

The wired-ANDing of the bus lines is used to solve both these problems. The serial

clocks from all masters will be wired-ANDed, yielding a combined clock with a high

period equal to the one from the master with the shortest high period. The low period of

the combined clock is equal to the low period of the master with the longest low period.

Note that all masters listen to the SCL line, effectively starting to count their SCL high

and low time-out periods when the combined SCL line goes high or low, respectively.

Figure 82. SCL Synchronization between Multiple Masters

Arbitration is carried out by all masters continuously monitoring the SDA line after out-

putting data. If the value read from the SDA line does not match the value the master

had output, it has lost the arbitration. Note that a master can only lose arbitration when it

outputs a high SDA value while another master outputs a low value. The losing master

should immediately go to slave mode, checking if it is being addressed by the winning

master. The SDA line should be left high, but losing masters are allowed to generate a

clock signal until the end of the current data or address packet. Arbitration will continue

until only one master remains, and this may take many bits. If several masters are trying

to address the same slave, arbitration will continue into the data packet.

low

high

SCL from

Master A

SCL from

Master B

SCL bus

Line

low

high

Masters Start

Counting Low Period

Masters Start

Counting High Period

ATMEGA16 датащи(PDF) 170 Page - ATMEL Corporation