SM8213 datasheet(12/33 Pages) NPC

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SM8213AM

NIPPON PRECISION CIRCUITS—12

Preamble mode

Preamble mode is a continuous 544-bit long period.

If neither a preamble pattern, rate error nor sync code

is detected during this period, operation transfers to

idle mode.

If a preamble pattern is detected, the preamble mode

544-bit long period is recommenced.

If the sync code is detected, AREA goes HIGH and

operation transfers to lock mode. If an error of 2 bits

or less occurs, the detected word is recognized as the

sync code. During the preamble mode interval, BS1

and BS3 are held HIGH. BS2 stays LOW.

Note that a single error occurs when two active edges

occur in the received signal on SIGNAL within 1-bit

unit time. A rate error occurs when the number of

errors in the error counter equals the error threshold

set by ﬂags ER0 to ER2. The error counter is reset

when a preamble pattern is detected.

Idle mode

In idle mode, a check is made for the presence of a

preamble signal when the RF intermittent-duty con-

trol signals (BS1, BS2, BS3) for battery saving are

active. If a preamble pattern is detected, operation

immediately transfers to preamble mode. If a pream-

ble pattern is not detected, intermittent-duty opera-

tion continues.

A preamble pattern is detected when either a 101010

or 010101 6-bit pattern is detected. Since there is a

reasonable probability that this simple pattern can

occur during a valid communicated signal (data, not

preamble), this 6-bit pattern makes returning to pre-

amble mode easier. This is useful for cases where

weak electric ﬁelds, noise or other temporary inter-

ference cause device operation to transfer to idle

mode.

Furthermore, the idle mode receive timing immedi-

ately after transfer from lock mode is the same as the

original sync code receive timing. As a result, if a

sync code is detected, operation returns to lock

mode.

Figure 5. Preamble mode internal operation

..1010111010101010..

Preamble Signal

Preamble count

starts

Counting

Count reset to 0

Preamble detected

Preamble count restarts

Error bit

t : 1-bit time

Error counter (e. g. set value

≥ 3)

Preamble and error

count starts

Preamble detected

and count reset

1 01 01 0 1

0 11 12 2 0

Figure 6. Idle mode timing

BS2

(flag BS2 option = 0)

BS1

62.5ms

(26.7ms)

[13.4ms]

1062.5ms (453.3ms) [226.7ms]

Receive timing

1.953*Nms

(0.833*Nms)

[0.417*Nms]

1.953*Mms

(0.833*Mms)

[0.417*Mms]

BS2

(flag BS2 option = 1)

BS3

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