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SM8213 датащи(PDF) 7 Page - Nippon Precision Circuits Inc

номер детали SM8213
подробное описание детали  POCSAG Decoder For Multiframe Pagers
PDF  33 Pages
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производитель  NPC [Nippon Precision Circuits Inc]
домашняя страница  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM8213 датащи(HTML) 7 Page - Nippon Precision Circuits Inc

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SM8213AM
NIPPON PRECISION CIRCUITS—7
FUNCTIONAL DESCRIPTION
Unless otherwise specified, values in diagrams with-
out parentheses are for 512 bps, in ( ) are for 1200
bps, and in [ ] are for 2400 bps. “M” represents the
value of PL5 (MSB) to PL0 (LSB), and “N” repre-
sents the value of RF5 (MSB) to RF0 (LSB).
Receive Format
The receive format conforms to CCIR RPC No. 1 (POCSAG).
Sync signal (SC)
The sync signal is a continuous code word in the
received signal, used for word synchronization. It
comprises 31 bits in an M-series bit pattern plus one
even-parity bit, making a 32-bit signal. The sync
code word pattern is shown in table 1.
Figure 1. Receive signal format
Sync Code Part
1 Batch
Frame Part
01
23
4
56
7
1 Code Word
Sync Code Part
SC
SC
7
0
Sync Code Word
1
32
Address bits
Function bits
Check bits
Message bits
12
19 20
21 22
31
32
0
1
Even - parity bit
Even - parity bit
Check bits
Address signal
Message signal
1 Frame(= 2 Code Words)
Preamble
1st Batch
2nd Batch
Frame No.
Continuous 575 - bit "1, 0" bit pattern
Sync
Code
Sync
Code
Table 1. Sync code format
Bit number
Bit value
Bit number
Bit value
Bit number
Bit value
Bit number
Bit value
1091
17
0
25
1
2
1
101180261
3
1
110190270
4
1
121201281
5
1
130210291
6
1
140221300
7
0
151230310
8
0
160241320



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