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SM8213 датащи(PDF) 9 Page - Nippon Precision Circuits Inc

номер детали SM8213
подробное описание детали  POCSAG Decoder For Multiframe Pagers
PDF  33 Pages
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производитель  NPC [Nippon Precision Circuits Inc]
домашняя страница  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM8213 датащи(HTML) 9 Page - Nippon Precision Circuits Inc

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SM8213AM
NIPPON PRECISION CIRCUITS—9
Idle signal
In the POCSAG format, for pager systems that send
numeric data, the message information content var-
ies and as a result an idle signal or another address
signal is inserted after the message to indicate the
end of the message.
That is, if no address word or message word exists
for a frame within a batch or for a code word within
a frame, the idle pattern, shown in table 3, is trans-
mitted in its place. Then during message signal
reception, the message ends when the idle signal is
detected.
The SM8213AM supports 2 methods of determining
the end of message. Namely, a message ends when
either an idle signal or another address is received
(POCSAG format), or when an interrupt signal from
the CPU is received.
Receive signal duty factor
During preamble detection, the preamble pattern
(1,0) is recognized at duty factors from 25% (min) to
75% (max) of the (1,0) preamble cycle.
Error correction and detection
The SM8213AM performs error correction (or
detection) on each code word as described in table 4.
Note that there are 8 selectable error correction con-
ditions for the preamble pattern.
An error is deemed to have occurred when 2 or more
signal edges occur within 1-bit unit time, and a rate
error is deemed to have occurred when the number of
errors exceeds the counter value. Refer to the “Pre-
amble Mode” section for a discussion of the error
counter.
Table 3. Idle code format
Bit number
Bit value
Bit number
Bit value
Bit number
Bit value
Bit number
Bit value
1091
17
1
25
1
2
1
100181260
3
1
110190270
4
1
120200281
5
1
131210290
6
0
140220301
7
1
150230311
8
0
161241321
Table 4. Error correction
Item
Description
Preamble Pattern Detection
Selectable 1 to 8 rate errors in 6 to 544 bits
Synchronization Code word
Detection 2 random errors in 32 bits
Self Address Code word
Detection 2 random errors in 32 bits
Message Code word
1-bit and 2-bit burst errors in 31 bits



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