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ISO5451DW датащи(PDF) 3 Page - Texas Instruments |
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ISO5451DW датащи(HTML) 3 Page - Texas Instruments |
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3 / 38 page ![]() 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 DESAT VEE2 VCC2 GND2 VEE2 VCC1 GND1 RDY IN- IN+ GND1 FLT RST NC OUT CLAMP ISO5451 www.ti.com SLLSEO1B – JUNE 2015 – REVISED DECEMBER 2015 5 Description (continued) The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input side and output side supplies. If either side has insufficient supply the RDY output goes low, otherwise this output is high. The ISO5451 is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to 125°C ambient. 6 Pin Configuration and Function DW Package 16-Pin SOIC Top View Pin Functions PIN I/O DESCRIPTION NAME NO. VEE2 1, 8 - Output negative supply. Connect to GND2 for Unipolar supply application. DESAT 2 I Desaturation voltage input GND2 3 - Gate drive common. Connect to IGBT emitter. NC 4 - Not connected VCC2 5 - Most positive output supply potential. OUT 6 O Gate drive voltage output CLAMP 7 O Miller clamp output GND1 9, 16 - Input ground IN+ 10 I Non-inverting gate drive voltage control input IN- 11 I Inverting gate drive voltage control input RDY 12 O Power-good output, active high when both supplies are good. FLT 13 O Fault output, low-active during DESAT condition RST 14 I Reset input, apply a low pulse to reset fault latch. VCC1 15 - Positive input supply (3 V to 5.5 V) Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ISO5451 |
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