ISO5451DW datasheet(5/38 Pages) TI

5 / 38 page

ISO5451

www.ti.com

SLLSEO1B – JUNE 2015 – REVISED DECEMBER 2015

7.4 Thermal Information

DW (SOIC)

THERMAL METRIC(1)

UNIT

16 PINS

RθJA

Junction-to-ambient thermal resistance

99.6

RθJC(top)

Junction-to-case (top) thermal resistance

48.5

RθJB

Junction-to-board thermal resistance

56.5

°C/W

ψJT

Junction-to-top characterization parameter

29.2

ψJB

Junction-to-board characterization parameter

56.5

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Power Rating

VALUE

UNIT

Maximum power dissipation(1)

1255

PID

Maximum input power dissipation

175

POD

Maximum output power dissipation

1080

(1)

Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of

251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design,

while ensuring that Junction temperature does not exceed 150°C.

7.6 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,

VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOLTAGE SUPPLY

Positive-going UVLO1 threshold voltage

VIT+(UVLO1)

2.25

input side (VCC1 – GND1)

Negative-going UVLO1 threshold voltage

VIT-(UVLO1)

1.7

input side (VCC1 – GND1)

UVLO1 Hysteresis voltage (VIT+ – VIT–)

VHYS(UVLO1)

0.24

input side

Positive-going UVLO2 threshold voltage

VIT+(UVLO2)

output side (VCC2 – GND2)

Negative-going UVLO2 threshold voltage

VIT-(UVLO2)

9.5

output side (VCC2 – GND2)

UVLO2 Hysteresis voltage (VIT+ – VIT–)

VHYS(UVLO2)

output side

IQ1

Input supply quiescent current

2.8

4.5

IQ2

Output supply quiescent current

3.6

LOGIC I/O

Positive-going input threshold voltage (IN+,

VIT+(IN,RST)

0.7 x VCC1

IN-, RST)

Negative-going input threshold voltage

VIT-(IN,RST)

0.3 x VCC1

(IN+, IN-, RST)

VHYS(IN,RST)

Input hysteresis voltage (IN+, IN-, RST)

0.15 x VCC1

IIH

High-level input leakage at (IN+) (1)

IN+ = VCC1

100

µA

IIL

Low-level input leakage at (IN-, RST) (2)

IN- = GND1, RST = GND1

-100

µA

IPU

Pull-up current of FLT, RDY

V(RDY) = GND1, V(FLT) = GND1

100

µA

VOL

Low-level output voltage at FLT, RDY

I(FLT) = 5 mA

0.2

GATE DRIVER STAGE

V(OUTPD)

Active output pull-down voltage

IOUT = 200 mA, VCC2 = open

V(OUTH)

High-level output voltage

IOUT = –20 mA

VCC2 - 0.5

VCC2 - 0.24

V(OUTL)

Low-level output voltage

IOUT = 20 mA

VEE2 + 13

VEE2 + 50

IN+ = high, IN- = low,

I(OUTH)

High-level output peak current

1.5

2.5

VOUT = VCC2 - 15 V

(1)

IIH for IN-, RST pin is zero as they are pulled high internally.

(2)

IIL for IN+ is zero, as it is pulled low internally.

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