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ISO5451DW датащи(PDF) 4 Page - Texas Instruments |
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ISO5451DW датащи(HTML) 4 Page - Texas Instruments |
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4 / 38 page ![]() ISO5451 SLLSEO1B – JUNE 2015 – REVISED DECEMBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC1 Supply voltage input side GND1 - 0.3 6 V VCC2 Positive supply voltage output side (VCC2 – GND2) –0.3 35 V VEE2 Negative supply voltage output side (VEE2 – GND2) –17.5 0.3 V V(SUP2) Total supply output voltage (VCC2 - VEE2) –0.3 35 V VOUT Gate driver output voltage VEE2 - 0.3 VCC2 + 0.3 V I(OUTH) Gate driver high output current Gate driver high output current 2.7 A (max pulse width = 10 μs, max duty I(OUTL) Gate driver low output current 5.5 A cycle = 0.2%) V(LIP) Voltage at IN+, IN-, FLT, RDY, RST GND1 - 0.3 VCC1 + 0.3 V I(LOP) Output current of FLT, RDY 10 mA V(DESAT) Voltage at DESAT GND2 - 0.3 VCC2 + 0.3 V V(CLAMP) Clamp voltage VEE2 - 0.3 VCC2 + 0.3 V TJ Junction temperature –40 150 °C TSTG Storage temperature -65 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability 7.2 ESD Ratings VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22- ±1500 C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC1 Supply voltage input side 3 5.5 V VCC2 Positive supply voltage output side (VCC2 – GND2) 15 30 V VEE2 Negative supply voltage output side (VEE2 – GND2) –15 0 V V(SUP2) Total supply voltage output side (VCC2 – VEE2) 15 30 V VIH High-level input voltage (IN+, IN-, RST) 0.7 x VCC1 VCC1 V VIL Low-level input voltage (IN+, IN-, RST) 0 0.3 x VCC1 V tUI Pulse width at IN+, IN- for full output (CLOAD = 1nF) 40 ns tRST Pulse width at RST for resetting fault latch 800 ns TA Ambient temperature -40 25 125 °C 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO5451 |
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