TMP007 datasheet(20/55 Pages) TI

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TMP007

SBOS685C – APRIL 2014 – REVISED JULY 2015

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7.3.8.9 Two-Wire Timing

The TMP007 is two-wire and SMBus compatible. Figure 23 to Figure 26 describe the various operations on the

TMP007. Parameters for Figure 23 are defined in Table 5. Bus definitions are:

Bus Idle

Both SDA and SCL lines remain high.

Start Data Transfer A change in the state of the SDA line, from high to low, while the SCL line is high defines a

start condition. Each data transfer is initiated with a start condition.

Stop Data Transfer A change in the state of the SDA line from low to high while the SCL line is high defines a

stop condition. Each data transfer is terminated with a repeated start or stop condition.

Data Transfer The number of data bytes transferred between a start and a stop condition is not limited, and is

determined by the master device.

The receiver acknowledges the transfer of data. It is also possible to use the TMP75B for

single-byte updates. To update only the MS byte, terminate communication by issuing a start

or stop condition on the bus.

Acknowledge Each receiving device, when addressed, must generate an acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock

pulse so that the SDA line is stable low during the high period of the acknowledge clock

pulse. Setup and hold times must be taken into account. When a master receives data, the

termination of the data transfer can be signaled by the master generating a not-acknowledge

(1) on the last byte transmitted by the slave.

Table 5. Two-Wire Timing Requirements

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

f(SCL)

SCL operating frequency

0.001

0.4

0.001

2.5

MHz

t(BUF)

Bus free time between stop and start condition

1300

260

t(HDSTA)

Hold time after repeated start condition.

600

160

After this period, the first clock is generated.

t(SUSTA)

Repeated start condition setup time

600

160

t(SUSTO)

Stop condition setup time

600

160

t(HDDAT)

Data hold time

900

150

t(SUDAT)

Data setup time

100

t(LOW)

SCL clock low period

1300

260

t(HIGH)

SCL clock high period

600

tF, tR – SDA

Data fall and rise time

300

tF, tR – SCL

Clock fall and rise time

300

Rise time for SCL

≤ 100 kHz

1000

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