TMP007 datasheet(18/55 Pages) TI

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TMP007

SBOS685C – APRIL 2014 – REVISED JULY 2015

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7.3.8 Serial Interface

The TMP007 operates only as a slave device on the serial bus. Connections to the bus are made using the SCL

Input and open-drain I/O SDA line. The SDA and SCL pins feature integrated spike suppression filters and

Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP007 supports the transmission

protocol for both fast and fastplus (1 kHz to 1 MHz) and high-speed (1 MHz to 2.5 MHz) mode. All data bytes are

transmitted MSB first. At higher speeds, thermal dissipation affects device operation, including accuracy.

7.3.8.1 Bus Overview

The device that initiates a transfer is called a master, and the devices controlled by the master are slaves. The

bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the start and stop conditions.

To address a specific device, a start condition is initiated, indicated by pulling the data-line (SDA) from a high-to-

low logic level while SCL is high. All slaves on the bus shift in the slave address byte, with the last bit indicating

whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds

to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data

transfer SDA must remain stable while SCL is high, as any change in SDA while SCL is high will be interpreted

as a control signal.

Once all data has been transferred, the master generates a stop condition, indicated by pulling SDA from low to

high while SCL is high.

7.3.8.2 Serial Bus Address

To communicate with the TMP007, the master must first address slave devices via a slave address byte. The

slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or

write operation. The TMP007 features two address pins allowing up to eight devices to be connected on a single

bus. Pin logic levels and the corresponding address values are described in Table 4.

Table 4. Address Pins and Slave Addresses

ADR1

ADR0

SMBus ADDRESSES

1000000

1000001

SDA

1000010

SCL

1000011

1000100

1000101

SDA

1000110

SCL

1000111

7.3.8.3 Writing and Reading Operations

Accessing a particular register on the TMP007 is accomplished by writing the appropriate value to the pointer

bit low. Every write operation to the TMP007 requires a value for the pointer register (see Figure 24).

When reading from the TMP007, the last value stored in the pointer register by a write operation is used to

determine which register is read by a read operation. To change the register pointer for a read operation, write a

new value to the pointer register. This action is accomplished by issuing a slave address byte with the R/W bit

low, followed by the pointer register byte. No additional data are required. The master then generates a start

condition and sends the slave address byte with the R/W bit high to initiate the read command. See Figure 25 for

details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually

send the pointer register byte because the TMP007 remembers the pointer register value until it is changed by

the next write operation.

Note that register bytes are sent most significant byte first, followed by the least significant byte.

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