ZL6105ALAF datasheet(10/35 Pages) INTERSIL

10 / 35 page

ZL6105

FN6906.5

December 19, 2013

ZL6105 Overview

Digital-DC Architecture

The ZL6105 is an innovative mixed-signal power conversion and

power management IC based on Zilker Labs patented Digital-DC

technology that provides an integrated, high performance

step-down converter for a wide variety of power supply

applications.

Today’s embedded power systems are typically designed for optimal

efficiency at maximum load, reducing the peak thermal stress by

limiting the total thermal dissipation inside the system.

Unfortunately, many of these systems are often operated at load

levels far below the peak where the power system has been

optimized, resulting in reduced efficiency. While this may not cause

thermal stress to occur, it does contribute to higher electricity usage

and results in higher overall system operating costs.

Zilker Labs’ efficiency-adaptive ZL6105 DC/DC controller helps

mitigate this scenario by enabling the power converter to

automatically change their operating state to increase efficiency

and overall performance with little or no user interaction needed.

Auto compensation is available to eliminate the need for manual

compensation of the PID filter.

Its unique PWM loop utilizes an ideal mix of analog and digital

blocks to enable precise control of the entire power conversion

process with no software required, resulting in a very flexible

device that is also very easy to use. An extensive set of power

management functions are fully integrated and can be

configured using simple pin connections. The user configuration

can be saved in an internal non-volatile memory (NVM).

Additionally, all functions can be configured and monitored via

the SMBus hardware interface using standard PMBus

commands, allowing ultimate flexibility.

Once enabled, the ZL6105 is immediately ready to regulate

power and perform power management tasks with no

programming required. Advanced configuration options and

real-time configuration changes are available via the I2C/SMBus

interface if desired and continuous monitoring of multiple

operating parameters is possible with minimal interaction from a

host controller. Integrated sub-regulation circuitry enables single

supply operation from any supply between 3V and 14V with no

secondary bias supplies needed.

The ZL6105 can be configured by simply connecting its pins

according to the tables provided in the following sections.

Additionally, a comprehensive set of development tools and

application notes are available to help simplify the design

process. An evaluation board is also available to help the user

become familiar with the device. This board can be evaluated as

a standalone platform using pin configuration settings. A

Windows™ based GUI is also provided to enable full configuration

and monitoring capability via the I2C/SMBus interface using an

available computer and the included USB cable.

Application notes are available to assist the user in designing to

specific application demands. Please visit www.intersil.com to

access the most up-to-date documentation.

Power Conversion Overview

The ZL6105 operates as a voltage-mode, synchronous buck

converter with a selectable constant frequency pulse width

modulator (PWM) control scheme that uses external MOSFETs,

capacitors, and an inductor to perform power conversion.

Figure 5 illustrates the basic synchronous buck converter

topology showing the primary power train components. This

converter is also called a step-down converter, as the output

voltage must always be lower than the input voltage. In its most

simple configuration, the ZL6105 requires two external

N-channel power MOSFETs, one for the top control MOSFET (QH)

and one for the bottom synchronous MOSFET (QL). The amount

of time that QH is on as a fraction of the total switching period is

known as the duty cycle D, which is described by Equation 1:

During time D, QH is on and VIN – VOUT is applied across the

inductor. The current ramps up as shown in Figure 6.

When QH turns off (time 1-D), the current flowing in the inductor

must continue to flow from the ground up through QL, during

which the current ramps down. Since the output capacitor COUT

exhibits a low impedance at the switching frequency, the AC

component of the inductor current is filtered from the output

voltage so the load sees nearly a DC voltage.

Typically, buck converters specify a maximum duty cycle that

effectively limits the maximum output voltage that can be realized

for a given input voltage. This duty cycle limit ensures that the

low-side MOSFET is allowed to turn on for a minimum amount of

time during each switching cycle, which enables the bootstrap

capacitor (CB in Figure 6) to be charged up and provide adequate

gate drive voltage for the high-side MOSFET. See “High-side Driver

VIN

VOUT

BST

COUT

CIN

FIGURE 5. SYNCHRONOUS BUCK CONVERTER

OUT

≈

(EQ. 1)

FIGURE 6. INDUCTOR WAVEFORM

TIME

1 - D

IN - VOUT

-V

OUT

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