ZL6105

6

FN6906.5

December 19, 2013

20

ISENA

I

Differential voltage input for current limit. High voltage tolerant.

21

VR

PWR

Internal 5V reference used to power internal drivers.

22

GL

O

Low side FET gate drive.

23

PGND

PWR

Power ground. Connect to low impedance ground plane.

24

SW

PWR

Drive train switch node.

25

GH

O

High-side FET gate drive.

26

BST

PWR

High-side drive boost voltage.

27

VDD (Note 3)

PWR

Supply voltage.

28

V25

PWR

Internal 2.5V reference used to power internal circuitry.

29

XTEMP

I

External temperature sensor input. Connect to external 2N3904 diode connected transistor.

30

DDC

I/O

Digital-DC Bus. (Open Drain) Interoperability between Zilker Labs devices.

31

MGN

I

Signal that enables margining of output voltage.

32

CFG1

I, M

Configuration pin. Used to setup clock synchronization and sequencing.

33

EN

I

Enable input (active high). Pull-up to enable PWM switching and pull-down to disable PWM switching.

34

PH_EN

I

Phase enable input (active high). Pull-up to enable phase and pull-down to disable phase for current

sharing.

35

CFG2

I, M

Configuration pin. Sets the phase offset (single-phase) or current sharing group position (multi-phase).

36

PG

O

Power-good output.

ePad

SGND

PWR

Exposed thermal pad. Common return for analog signals; internal connection to SGND. Connect to low

impedance ground plane.

NOTES:

1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pin dependents. (Refer to “Multi-mode Pins” on page 11).

2. The SYNC pin can be used as a logic pin, a clock input or a clock output.

PIN

LABEL

TYPE (Note 1)

DESCRIPTION

Ordering Information

PART NUMBER

(Notes 5, 6)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ZL6105ALAF

6105

-40 to +85

36 Ld QFN

L36.6x6C

ZL6105ALAFT (Note 4)

6105

-40 to +85

36 Ld QFN

L36.6x6C

ZL6105ALAFTK (Note 4)

6105

-40 to +85

36 Ld QFN

L36.6x6C

NOTES:

4. Please refer to TB347 for details on reel specifications.

5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-

free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

6. For Moisture Sensitivity Level (MSL), please see device information page for ZL6105. For more information on MSL please see techbrief TB363.