ZL6105

3

FN6906.5

December 19, 2013

Typical Application Circuit

The following application circuit represents a typical implementation of the ZL6105. For enable using the PMBus, it is recommended to

tie the enable pin (EN) to SGND.

ZL6105

1

2

3

4

5

6

7

8

9

27

26

25

24

23

22

21

20

19

DGND

SYNC

SA0

SA1

ILIM

CFG0

SCL

SDA

SALRT

VDD

BST

GH

SW

PGND

GL

VR

ISENA

ISENB

10 µF

4 V

3 x 10 µF

25 V

POWER GOOD OUTPUT

DB

BAT54

CB

1 µF

16 V

QH

QL

2.2 µH

2 x 47 µF

6.3 V

4.7 µF

6.3 V

RTN

EPAD

12V

V25

470 µF

2.5 V

POS-CAP

2*220 µF

6.3 V

100 m

ENABLE

Ground unification

4.7 µF

25 V

Notes:

1. Ferrite bead is optional for input noise suppression

3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices

connected). The 10 k

default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise time. Please refer to the

DDC Bus section for more details.

PHASE ENABLE

FIGURE 3. 12V TO 1.8V/16A APPLICATION CIRCUIT

Ω