UCD3138ARMHT datasheet(46/83 Pages) TI

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Digital Comparator 0

Control

Digital Comparator 1

Control

Digital Comparator 2

Control

Digital Comparator 3

Control

Front End

Control 0

Front End

Control 1

Front End

Control 2

Analog

Comparator 0

Analog Comparator 0

Control

Analog

Comparator 1

Analog Comparator 1

Control

Analog

Comparator 2

Analog Comparator 2

Control

Analog

Comparator 3

Analog Comparator 3

Control

Analog

Comparator 4

Analog Comparator 4

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Analog

Comparator 5

Analog Comparator 5

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Analog

Comparator 6

Analog Comparator 6

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External GPIO

Detection

fault[2:0]

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Fault Control

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Fault Control

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Fault Control

Analog Comparator

Automated Ramp

DCM Detection

HFO/LFO

Fail Detect

UCD3138A

SLUSC66B – MARCH 2015 – REVISED MAY 2015

www.ti.com

Figure 6-17. Fault Mux Block Diagram

6.10 Communication Ports

6.10.1 SCI (UART) Serial Communication Interface

A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous

Receiver/Transmitter pre-scaler (UART) interfaces are included within the device for asynchronous start-

stop serial data communication (see the pin out sections for details) Each interface has a 24 bit for

supporting programmable baud rates and has programmable data word and stop bit options. Half or full

duplex operation is configurable through register bits. A loop back feature can also be setup for firmware

verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being

used. Both the UART ports support Hardware auto baud correction improving robustness in

communication even at higher baud rates.

6.10.2 PMBUS

The PMBus Interface supports independent master and slave modes controlled directly by firmware

through a processor bus interface. Individual control and status registers enable firmware to send or

receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I2C

Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol

Specification (PMBus 1.3).

The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit

address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write

enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading

and writing of data and active-low write and output enable control signals. In addition, the PMBus Interface

connects directly to the I2C/SMBus/PMBus Clock, Data, Alert, and Control signals.

Example: PMBus Address Decode via ADC12 Reading

The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address

decoding. At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is

captured by the internal 12-bit ADC.

Detailed Description

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