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LTC1286CS8 датащи(PDF) 23 Page - Linear Technology |
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LTC1286CS8 датащи(HTML) 23 Page - Linear Technology |
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23 / 24 page ![]() 23 LTC1286/LTC1298 A “Quick Look” Circuit for the LTC1286 Users can get a quick look at the function and timing of the LT1286 by using the following simple circuit (Figure 13). VREF is tied to VCC. VIN is applied to the +IN input and the –IN input is tied to the ground. CS is driven at 1/16 the clock rate by the 74C161 and DOUT outputs the data. The output data from the DOUT pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 14). Note the LSB data is partially clocked out before CS goes high. TYPICAL APPLICATIONS N Micropower Battery Voltage Monitor A common problem in battery systems is battery voltage monitoring. This circuit monitors the 10 cell stack of NiCad or NiMH batteries found in laptop computers. It draws only 67 µA from the 5V supply at fSMPL = 0.1kHz and 25µA to 55 µA from the battery. The 12-bits of resolution of the LTC1286 are positioned over the desired range of 8V to 16V. This is easily accomplished by using the ADC’s differential inputs. Tying the –input to the reference gives an ADC input span of VREF to 2VREF (2.5V to 5V). The resistor divider then scales the input voltage for 8V to 16V. Figure 13. “Quick Look” Circuit for the LTC1286 CLR CLK A B C D P GND VCC RC QA QB QC QD T LOAD 74C161 VIN TO OSCILLOSCOPE CLOCK IN 250kHz LTC1286/98 F13 VCC CLK DOUT LTC1286 +IN –IN GND 4.7 µF 5V 5V VREF CS Figure 14. Scope Trace the LTC1286 “Quick Look” Circuit Showing A/D Output 101010101010 (AAAHEX) Figure 15. Micropower Battery Voltage Monitor 39k 5V LT1004-2.5 200k 91k 3 Ω BATTERY MONITOR INPUT 8V TO 16V 1 µF 0.1 µF CS CLK DOUT LTC1286 LTC1286/98 F15 –IN VCC VREF GND +IN MSB (B11) VERTICAL: 5V/DIV HORIZONTAL: 10µs/DIV LSB (B0) NULL BIT LTC1286/98 F14 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights. |
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