LTC1286CS8 datasheet(22/24 Pages) LINER

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LTC1286/LTC1298

TYPICAL APPLICATIONS N

Interfacing to the Parallel Port of the INTEL 8051

Family

The Intel 8051 has been chosen to demonstrate the

interface between the LTC1298 and parallel port micro-

processors. Normally the CS, CLK and DIN signals would

be generated on 3 port lines and the DOUT signal read on

a 4th port line. This works very well. However, we will

demonstrate here an interface with the DIN and DOUT of the

LTC1298 tied together as described in the SERIAL INTER-

FACE section. This saves one wire.

The 8051 first sends the start bit and MUX address to the

LTC1298 over the data line connected to P1.2. Then P1.2

is reconfigured as an input (by writing to it a one) and the

8051 reads back the 12-bit A/D result over the same data

line.

LABEL

MNEMONIC

OPERAND

COMMENTS

MOV

A, #FFH

DIN word for LTC1298

SETB

P1.4

Make sure CS is high

CLR

P1.4

CS goes low

MOV

R4, #04

Load counter

LOOP 1

RLC

Rotate DIN bit into Carry

CLR

P1.3

SCLK goes low

MOV

P1.2, C

Output DIN bit to LTC1298

SETB

P1.3

SCLK goes high

DJNZ

R4, LOOP 1

Next bit

MOV

P1, #04

Bit 2 becomes an input

CLR

P1.3

SCLK goes low

MOV

R4, #09

Load counter

LOOP 2

MOV

C, P1.2

Read data bit into Carry

RLC

Rotate data bit into Acc.

SETB

P1.3

SCLK goes high

CLR

P1.3

SCLK goes low

DJNZ

R4, LOOP 2

Next bit

MOV

R2, A

Store MSBs in R2

CLR

Clear Acc.

MOV

R4, #04

Load counter

LOOP 3

MOV

C, P1.2

Read data bit into Carry

RLC

Rotate data bit into Acc.

SETB

P1.3

SCLK goes high

CLR

P1.3

SCLK goes low

DJNZ

R4, LOOP 3

Next bit

MOV

R4, #04

Load counter

LOOP 4

RRC

Rotate right into Acc.

DJNZ

R4, LOOP 4

Next Rotate

MOV

R3, A

Store LSBs in R3

SETB

P1.4

CS goes high

DOUT FROM 1298 STORED IN 8501 RAM

MSB

B11 B10 B9

B8 B7 B6 B5 B4

LSB

B1 B0 0

CLK

DOUT

DIN

LTC1298

ANALOG

INPUTS

P1.4

P1.3

P1.2

8051

MUX ADDRESS

A/D RESULT

LTC1286/98 TA01

CLK

MSBF BIT LATCHED

INTO LTC1298

8051 P1.2 OUTPUTS DATA

TO LTC1298

LTC1298 SENDS A/D RESULT

BACK TO 8051 P1.2

LTC1298 TAKES CONTROL OF DATA

LINE ON 4TH FALLING CLK

8051 P1.2 RECONFIGURED

AS IN INPUT AFTER THE 4TH RISING CLK

AND BEFORE THE 4TH FALLING CLK

MSBF

B11

B10

SGL/

DIFF

START

DATA

(DIN/DOUT)

LTC1286/98 TA02

ODD/

SIGN

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