LTC1286CS8 datasheet(10/24 Pages) LINER

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LTC1286/LTC1298

APPLICATION INFORMATION

SERIAL INTERFACE

The 2-channel LTC1298 communicates with micropro-

cessors and other external circuitry via a synchronous,

half duplex, 4-wire serial interface. The single channel

LTC1286 uses a 3-wire interface (see Operating Sequence

in Figures 1 and 2).

Data Transfer

The CLK synchronizes the data transfer with each bit being

transmitted on the falling CLK edge and captured on the

rising CLK edge in both transmitting and receiving systems.

The LTC1286 does not require a configuration input word

and has no DIN pin. A falling CS initiates data transfer as

shown in the LTC1286 operating sequence. After CS falls

the second CLK pulse enables DOUT. After one null bit the

A/D conversion result is output on the DOUT line. Bringing

CS high resets the LTC1286 for the next data exchange.

The LTC1298 first receives input data and then transmits

back the A/D conversion result (half duplex). Because of

the half duplex operation, DIN and DOUT may be tied

together allowing transmission over just 3 wires: CS, CLK

and DATA (DIN/DOUT).

Data transfer is initiated by a falling chip select (CS) signal.

After CS falls the LTC1298 looks for a start bit. After the

start bit is received, the 3-bit input word is shifted into the

DIN input which configures the LTC1298 and starts the

conversion. After one null bit, the result of the conversion

is output on the DOUT line. At the end of the data exchange

CS should be brought high. This resets the LTC1298 in

preparation for the next data exchange.

CLK

tCYC

B11

B10

B11

HI-Z

DOUT

tCONV

tDATA

HI-Z

tsuCS

NULL

BIT

POWER

DOWN

POWER DOWN

B0*

NULL

BIT

B10

tSMPL

(MSB)

CLK

tCYC

B11*

B10

B11

HI-Z

DOUT

tCONV

tDATA

HI-Z

tsuCS

NULL

BIT

LTC1286/98 • F01

B10

tSMPL

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,

THE ADC WILL OUTPUT ZEROS INDEFINITELY.

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,

THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.

tDATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT

BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.

Figure 1. LTC1286 Operating Sequence

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