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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RM0312 датащи(PDF) 244 Page - STMicroelectronics |
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RM0312 датащи(HTML) 244 Page - STMicroelectronics |
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244 / 275 page  Universal synchronous/asynchronous receiver transmitter (USART) RM0312 244/275 DocID022352 Rev 3 21.6.2 Data register (USART_DR) Address offset: 0x01 Reset value: 0xXX Bit 1 FE: Framing error (4) This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (a read to the USART_SR register followed by a read to the USART_DR register). 0: No framing error is detected 1: Framing error or break character is detected Bit 0 PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by a read to the USART_DR data register). You have to wait for the RXNE flag to be set before clearing it. An interrupt is generated if PIEN=1 in the USART_CR1 register. 0: No parity error 1: Parity error 1. The IDLE bit is not set again until the RXNE bit has been set itself (i.e. a new idle line occurs) 2. When this bit is set, the RDR register content is not lost but, the shift register is overwritten. 3. This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. 4. This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. If the word currently being transferred causes both a frame error and an overrun error, it is transferred and only the OR bit is set. 7 654 3210 DR[7:0] rw Bits 7:0 DR[7:0]: Data value Contains the received or transmitted data character, depending on whether it is read from or written to. The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR) The TDR register provides the parallel interface between the internal bus and the output shift register. The RDR register provides the parallel interface between the input shift register and the internal bus. |
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