RM0312 datasheet(246/275 Pages) STMICROELECTRONICS

246 / 275 page

Universal synchronous/asynchronous receiver transmitter (USART)

RM0312

246/275

DocID022352 Rev 3

21.6.5

Control register 1 (USART_CR1)

Address offset: 0x04

Reset value: 0x00

654

3210

USARTD

WAKE

PCEN

PIEN

Bit 7 R8: Receive data bit 8

This bit is used to store the 9th bit of the received word when M=1

Bit 6 T8: Transmit data bit 8

This bit is used to store the 9th bit of the transmitted word when M=1

Bit 5 USARTD: USART disable (for low power consumption)

When this bit is set the USART prescaler and outputs are stopped at the end of the current byte

transfer in order to reduce power consumption. This bit is set and cleared by software.

0: USART enabled

1: USART prescaler and outputs disabled

Bit 4 M: word length

This bit determines the word length. It is set or cleared by software.

0: 1 Start bit, 8 Data bits, ‘n’ STOP bit (n depending on STOP[1:0] bits in the USART_CR3 register)

1: 1 Start bit, 9 Data bits, 1 STOP bit

Note: The M bit must not be modified during a data transfer (both transmission and reception)

Bit 3 WAKE: Wakeup method

This bit determines the USART wakeup method, it is set or cleared by software.

0: Idle line

1: Address mark

Bit 2 PCEN: Parity control enable

This bit selects the hardware parity control (generation and detection). When the parity control is

enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is

checked on the received data. This bit is set and cleared by software. Once it is set, PCEN is active

after the current byte (in reception and in transmission).

0: Parity control disabled

1: Parity control enabled

Bit 1 PS: Parity selection

This bit selects the odd or even parity when the parity generation/detection is enabled (PCEN bit set).

It is set and cleared by software. The parity will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 0 PIEN: Parity interrupt enable

This bit is set and cleared by software.

0: Parity interrupt disabled

1: Parity interrupt is generated whenever PE=1 in the USART_SR register

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