RM0312 datasheet(248/275 Pages) STMICROELECTRONICS

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Universal synchronous/asynchronous receiver transmitter (USART)

RM0312

248/275

DocID022352 Rev 3

21.6.7

Control register 3 (USART_CR3)

Address offset: 0x06

Reset value: 0x00

654

3210

Reserved

STOP[1:0]

CLKEN

CPOL

CPHA

LBCL

Bit 7:6 Reserved

Bits 5:4 STOP: STOP bits

These bits are used for programming the STOP bits.

00: 1 STOP bit

01: Reserved

10: 2 STOP bits

11: Reserved

Bit 3 CLKEN: Clock enable

This bit allows the user to enable the USART_CK pin.

0: USART_CK pin disabled

1: USART_CK pin enabled

Bit 2 CPOL: Clock polarity(1)

This bit allows the user to select the polarity of the clock output on the USART_CK pin. It works in

conjunction with the CPHA bit to produce the desired clock/data relationship

0: USART_CK to 0 when idle

1: USART_CK to 1 when idle.

Bit 1 CPHA: Clock phase (1)

This bit allows the user to select the phase of the clock output on the USART_CK pin. It works in

conjunction with the CPOL bit to produce the desired clock/data relationship

0: The first clock transition is the first data capture edge

1: The second clock transition is the first data capture edge

Bit 0 LBCL: Last bit clock pulse(1)(2)

This bit allows the user to select whether the clock pulse associated with the last data bit transmitted

(MSB) has to be output on the USART_CK pin.

0: The clock pulse of the last data bit is not output to the USART_CK pin.

1: The clock pulse of the last data bit is output to the USART_CK pin.

1. These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.

2. The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by the M bit in the USART_CR1

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