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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RM0312 датащи(PDF) 245 Page - STMicroelectronics |
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RM0312 датащи(HTML) 245 Page - STMicroelectronics |
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245 / 275 page  DocID022352 Rev 3 245/275 RM0312 Universal synchronous/asynchronous receiver transmitter (USART) 249 21.6.3 Baud rate register 1 (USART_BRR1) The baud rate registers are common to both the transmitter and the receiver. The baud rate is programmed using two registers BRR1 and BRR2. Writing of BRR2 (if required) should precede BRR1, since a write to BRR1 will update the baud counters. See Figure 87: How to code USART_DIV in the BRR registers on page 235 and Table 46: Baud rate programming and error calculation on page 236. Note: The baud counters stop counting if the TEN or REN bits are disabled respectively. Address offset: 0x02 Reset value: 0x00 21.6.4 Baud rate register 2 (USART_BRR2) Address offset: 0x03 Reset value: 0x00 7 654 3210 USART_DIV[11:4] rw rw rw rw - rw rw rw Bits 7:0 USART_DIV[11:4]: USART_DIV bits (1) These 8 bits define the 2nd and 3rd nibbles of the 16-bit USART divider (USART_DIV). 1. BRR1 = 0x00 means USART clock is disabled. 7 654 3210 USART_DIV[15:12] USART_DIV[3:0] rw rw Bits 7:4 USART_DIV[15:12]: MSB of USART_DIV These 4 bits define the MSB of the USART Divider (USART_DIV) Bits 3:0 USART_DIV[3:0]: LSB of USART_DIV These 4 bits define the LSB of the USART Divider (USART_DIV) |
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