PM0214 datasheet(217/245 Pages) STMICROELECTRONICS

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DocID022708 Rev 4

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PM0214

Core peripherals

244

4.4.8

System handler priority registers (SHPRx)

The SHPR1-SHPR3 registers set the priority level, 0 to 255 of the exception handlers that

have configurable priority.

SHPR1-SHPR3 are byte accessible.

The system fault handlers and the priority field and register for each handler are:

Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of each field,

and bits[3:0] read as zero and ignore writes (where M=4).

System handler priority register 1 (

SHPR1)

Address offset: 0x18

Reset value: 0x0000 0000

Required privilege: Privileged

System handler priority register 2 (SHPR2)

Address offset: 0x1C

Reset value: 0x0000 0000

Required privilege: Privileged

Table 52. System fault handler priority fields

Handler

Field

Memory management fault

PRI_4

System handler priority register 1 (SHPR1)

Bus fault

PRI_5

Usage fault

PRI_6

SVCall

PRI_11

System handler priority register 2 (SHPR2) on

page 217

PendSV

PRI_14

System handler priority register 3 (SHPR3) on

page 218

SysTick

PRI_15

3029

Reserved

PRI_6[7:4]

PRI_6[3:0]

PRI_5[7:4]

PRI_5[3:0]

PRI_4[7:4]

Bits 31:24

Reserved, must be kept cleared

Bits 23:16

PRI_6: Priority of system handler 6, usage fault

Bits 15:8

PRI_5: Priority of system handler 5, bus fault

Bits 7:0

PRI_4: Priority of system handler 4, memory management fault

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