PM0214 datasheet(180/245 Pages) STMICROELECTRONICS

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Core peripherals

PM0214

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DocID022708 Rev 4

4.2.1

MPU access permission attributes

This section describes the MPU access permission attributes. The access permission bits,

TEX, C, B, S, AP, and XN, of the MPU_RASR register, control access to the corresponding

memory region. If an access is made to an area of memory without the required

permissions, then the MPU generates a permission fault.

Table 39 shows the encodings for the TEX, C, B, and S access permission bits.

Table 40 shows the cache policy for memory attribute encodings with a TEX value is in the

range 4-7.

Table 39. TEX, C, B, and S encoding

TEX

Memory type

Shareability

Other attributes

b000

0x (1)

1. THe MPU ignores the value fo this bit.

Strongly-ordered

Shareable

x(1) Device

Shareable

Normal

Not shareable Outer and inner write-through. No

write allocate.

Shareable

Normal

Not shareable Outer and inner write-back. No write

allocate.

Shareable

b001

Normal

Not shareable

Outer and inner noncacheable.

Shareable

x(1) Reserved encoding

x(1) Implementation defined attributes.

Normal

Not shareable Outer and inner write-back. Write

and read allocate.

Shareable

b010

x(1) Device

Not shareable Nonshared Device.

x(1) Reserved encoding

1x(1)

x(1) Reserved encoding

b1BB

Normal

Not shareable Cached memory(2) , BB = outer

policy, AA = inner policy.

2. See Table 40 for the encoding of the AA and BB bits.

Shareable

Table 40. Cache policy for memory attribute encoding

Encoding, AA or BB

Corresponding cache policy

Non-cacheable

Write back, write and read allocate

Write through, no write allocate

Write back, no write allocate

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