Class B solution structure

AN3181

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Doc ID 17286 Rev 2

routine. The user must force the reset vector to the first address in STL_StartUp() routine.

The startup tests block structure is shown in Figure 5 and includes the following self tests:

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Watch dogs startup test

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CPU startup test

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Flash complete checksum test

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Full RAM March C-/X test

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Clock startup test

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Control flow checks

These blocks are described in more details in the next chapters. User can control including

them as usual in the configuration file stm8_stl_param.h.

Figure 5.

startup self tests structure

4.2.1

Watchdog startup self test

The first startup self test is to enter WDG self test routine. The program passes through this

routine three times. First the routine checks the reset source in reset status register. If

Independent watchdog (IWDG) is not flagged in reset status register, then reset sources is

cleared and IWDG test begins. The IWDG is set to the shortest period and the

microcontroller is reset by hardware and IWDG flag is set (see Figure 6). The routine comes

back to the beginning and check WDG flags. When IWDG is recognized, it looks for WWDG

flag. If WWDG is not flagged, the test continues a second time with window watchdog

(WWDG) test. Again the microcontroller is reset by hardware and WWDG flag is set. When

both WDG flags are set in the reset status register, the test is assumed as finished and both

flags are cleared. WWDG is not present at STM8L10x devices, so WWDG test is not

present.

User must carefully set both IWDG and WWDG periods. Time periods and window refresh

parameters must be set according to the time base interval because refresh is done at the

successful end of the periodical run mode test in main loop.