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UPD62AMC датащи(PDF) 50 Page - NEC |
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UPD62AMC датащи(HTML) 50 Page - NEC |
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50 / 62 page ![]() 50 µPD62A Data Sheet U14474EJ1V0DS00 AC Characteristics (TA = –40 to +85˚C, VDD = 2.0 to 3.6 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Instruction execution time tCY 7.9 27 µs KI, S0, S1 high-level width tH 10 µs When releasing In HALT mode 10 µs standby mode In STOP mode Note µs RESET low-level width tRSL 10 µs Note 10 + 52/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillation frequency) POC Circuit (mask optionNote 1) (TA = –40 to +85˚C) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit POC-detected voltageNote 2 VPOC 1.85 2.0 V Notes 1. Operates effectively under the conditions of fX = 2.4 to 8 MHz. 2. Refers to the voltage at which the POC circuit cancels an internal reset. If VPOC < VDD, the internal reset is released. From the time of VPOC ≥ VDD until the internal reset takes effect, a delay of up to 1 ms occurs. When the period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = –40 to +85˚C, VDD = 2.0 to 3.6 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Oscillation frequency fX 2.4 3.64 8.0 MHz (ceramic resonator) |
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