AN4650 datasheet(78/102 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

AN4650

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DocID027415 Rev 1

Table 63. FIFO mode selection

8.1.6

FIFO_STATUS1 (3Ah)

The FIFO_STATUS1 register, together with the FIFO_STATUS2 register, provides

information about the number of samples stored in the FIFO. Each sample is represented as

16-bit data.

8.1.7

FIFO_STATUS2 (3Bh)

The FIFO_STATUS2 register, together with the FIFO_STATUS1 register, provides

information about the number of samples stored in the FIFO and about the current status

(threshold, overrun, full, empty) of the FIFO buffer.



FTH represents the watermark status. This bit is set high when the number of bytes

stored in the FIFO is equal to or higher than the watermark level (each sample is

represented as 16-bit data). The watermark status can be driven to the two interrupt

pins by setting to 1 the INT1_FTH bit of the INT1_CTRL register or the INT2_FTH bit of

the INT2_CTRL register.



FIFO_OVER_RUN is set high when the FIFO is completely filled and at least one

sample has already been overwritten to store the new data. This signal can be driven to

FIFO_MODE [2:0]

Configuration

000

Bypass mode. FIFO disabled.

001

FIFO mode. Stops collecting data when FIFO is full.

010

Reserved

011

Continuous mode until trigger is deasserted, then FIFO

mode.

100

Bypass mode until trigger is deasserted, then Continuous

mode.

101

Reserved

110

Continuous mode. If the FIFO is full, the new sample

overwrites the older one.

111

Reserved

Table 64. FIFO_STATUS1 register

DIFF_

FIFO_7

DIFF_

FIFO_6

DIFF_

FIFO_5

DIFF_

FIFO_4

DIFF_

FIFO_3

DIFF_

FIFO_2

DIFF_

FIFO_1

DIFF_

FIFO_0

Table 65. FIFO_STATUS2 register

FTH

FIFO_

OVER_RUN

FIFO_

FULL

FIFO_

EMPTY

DIFF_

FIFO_11

DIFF_

FIFO_10

DIFF_

FIFO_9

DIFF_

FIFO_8

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