AN4650 datasheet(73/102 Pages) STMICROELECTRONICS

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AN4650

First-in first-out (FIFO) buffer

102

First-in first-out (FIFO) buffer

In order to limit intervention by the host processor and facilitate post-processing data for

event recognition, the LSM6DS3 embeds an 8 kbyte first-in first-out buffer (FIFO).

The FIFO can be configured to store the following data:



gyroscope sensor data;



accelerometer sensor data;



external sensors (connected to sensor hub interface) data;



step counter and time stamp data;



temperature sensor data.

Saving data in the FIFO buffer is based on four ‘FIFO data set’ consisting of 6 bytes each:



The 1st FIFO data set is reserved for gyroscope data;



The 2nd FIFO data set is reserved for accelerometer data;



The 3rd FIFO data set is reserved for the external sensor data stored in the registers

from SENSORHUB1_REG to SENSORHUB6_REG (see Section 6.2.9 for details on

the SENSORHUBx_REG);



The 4th FIFO data set can be alternately associated to the external sensor data stored

in the registers from SENSORHUB7_REG to SENSORHUB12_REG, to the step

counter and time stamp info, or to the temperature sensor data.

All these data sets can be stored in FIFO at different ODRs, by setting the decimation

factors in the FIFO_CTRL3 and FIFO_CTRL4 registers. Decimation factors are also used to

select which FIFO data sets have to be stored in FIFO.

Five different FIFO operating modes can be chosen through the FIFO_MODE_[2:0] bits of

the FIFO_CTRL5 register:



Bypass mode;



FIFO mode;



Continuous mode;



Continuous-to-FIFO mode;



Bypass-to-Continuous mode.

Data are retrieved from the FIFO through two dedicated registers: FIFO_DATA_OUT_L and

FIFO_DATA_OUT_H. In this way, data can be read either from the FIFO (at a slower ODR)

or from the device output registers (at the normal ODR).

To monitor the FIFO status (full, empty, number of sample stored, etc), four dedicated

registers are available: FIFO_STATUS1, FIFO_STATUS2, FIFO_STATUS3,

FIFO_STATUS4.

Programmable FIFO thresholds can be set in FIFO_CTRL1 and FIFO_CTRL2 using the

FTH [11:0] bits.

FIFO full, FIFO threshold and FIFO overrun events can be enabled to generate dedicated

interrupts on the two interrupt pins (INT1 and INT2) through the INT1_FULL_FLAG,

INT1_FTH and INT1_OVR bits of the INT1_CTRL register, and through the

INT2_FULL_FLAG, INT2_FTH and INT2_OVR bits of the INT2_CTRL register.

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