AN3316 datasheet(25/42 Pages) STMICROELECTRONICS

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AN3316

Device modes

Doc ID 18232 Rev 2

25/42

For the HW steps, refer to Section : Common HW aspects. Now, see in details the operation

done for each phase:

RUN0 mode:

Mode config in HALT:

ME_HALT_MC.CFLAON = 2

(code Flash in Low Power mode)

ME_HALT_MC.DFLAON = 2

(data Flash in Low Power mode)

In this way, at HALT exiting, Flash startup from Low Power to Normal mode is very fast

as it takes less than 1 usec

ME_ HALT_MC.XOSC0ON = 1 (turn-on the XTAL)

ME HALT_MC.PLL0ON = 1

(turn-on the PLL)

ME_ HALT_MC.SYSCLK = 4

(set PLL as device system clock)

Periphs mode config HALT mode:

ME_RUN_LP0.HALT = 1 (activate low power peripheral configuration ’0’ in HALT)

ME_PCTL[4].LP_CFG = 0 to select the low power peripheral configuration ’0’ for

DSPI0 identified by offset = 4 (refer to figure x)

ME_PCTL[32].LP_CFG = 0 to select the low power peripheral configuration ’0’ for ADC

identified by offset = 32 (refer to figure x)

ME_PCTL[16].LP_CFG = 0 to select the low power peripheral configuration ’0’ for

FlexCAN0 identified by offset = 16 (refer to figure x)

Timer config:

See Step 5 (RUN0

 HALT mode)

Request transition to RUN0 mode:

So, in case of RUN0

 HALT transition, these two register writing should be done:

ME.MCTL.R = 0x80005AF0

ME.MCTL.R = 0x8000A50F

Table 7.

Peripherals clock source

Peripheral

(base = 0xC3FDC0C0)

Peripheral set

RPP_ZOH Platform

None (managed through ME

mode)

—

DSPin

4 + n

FlexCANn

16 + n

BAM

None (31 reserved)

—

ADC

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