AN3316 datasheet(17/42 Pages) STMICROELECTRONICS

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AN3316

Device modes

Doc ID 18232 Rev 2

17/42

Figure 8.

HW failure example

Error modes management

Mode Entry Module can generate an interrupt on the following events:

●

Invalid mode configuration:

following rules should be respected in order to prevent error configuration event:

–

IRC should be ON if: sysclk = rc_clk or sysclk = rc_clk_div

–

XOSC should be ON if: sysclk = osc_clk or sysclk = osc_clk_div

–

PLL should be ON if: sysclk = pll_clk

–

Configuration "00" for the CFLAON and DFLAON bit fields should not be used

–

MVR must be ON if any of the following is active: PLL/CFLASH/DFLASH

–

System clock configurations marked as ’reserved’ may not be selected

–

Configuration "1111" for the SYSCLK bit field is allowed only for STOP0 and TEST

modes

If one of the previous rule is violated, I_ICONF bit in the Interrupt Status register ME_IS is

set

●

Invalid mode transition

Following cases should be avoided to complete the transition properly:

–

Mode requested when a transition is active (mode transition illegal)

–

Target mode not valid with respect to the current (mode request illegal)

–

Target mode is disabled in mode enable register (disable mode access)

–

Target mode doesn’t exist (non existing mode access)

previous cases are signaled by ME_IMTS register.

2.4

Application cases

This chapter tries to show most significant transition cases managed by mode Entry

Module.

Except for the Power-On Reset phase that is performed through a completely HW transition

(RESET

 DRUN), transitions have either HW or SW aspects in the others cases.

XOSC failure

SAFE

DRUN

RUN0

svsclk = IRC

svsclk = XOSC

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