70353C datasheet(8/76 Pages) MICROCHIP

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dsPIC33E/PIC24E Family Reference Manual

DS70353C-page 21-8

21.3

ECAN REGISTERS

The ECAN module has a large number of Special Function Registers (SFRs) that are used to

configure the message acceptance filters and the message buffers. To enable effective use of

data RAM space, multiple sets of SFRs are mapped onto the same set of memory addresses.

The SFR Map Window Select bit (WIN) in ECAN Control Register 1 (CiCTRL1<0>) is used to

selectively access one of these sets of SFRs.

If CiCTRL1<0> = 1, the message acceptance filters, masks and filter buffer pointer registers are

accessed by the user application.

If CiCTRL1<0> = 0, the buffer control and status registers, and the transmit and receive data

registers are accessed by the user application.

21.3.1

ECAN Baud Rate Control Registers

• CiCFG1: ECAN Baud Rate Configuration Register 1

This register contains control bits to set the period of each time quantum (TQ), using the

baud rate prescaler, and specifies synchronization jump width in terms of time quanta (see

• CiCFG2: ECAN Baud Rate Configuration Register 2

This register is used to program the number of time quanta in each CAN bit segment,

including the propagation, and phase segments 1 and 2 (see Register 21-2).

21.3.2

ECAN Message Filter Registers

• CiFEN1: ECAN Acceptance Filter Enable Register

This register enables/disables acceptance filters 0-15 for message filtering (see

• CiRXFnSID: ECAN Acceptance Filter Standard Identifier Register n (n = 0-15)

These 16 registers specify the standard identifier (SID) for acceptance filters 0-15. The

identifier bits are selectively masked against the incoming message identifier to determine

if the message should be accepted or rejected (see Register 21-4). These registers are only

accessible by the user application when the WIN bit is set (CiCTRL1<0> = 1 = use buffer

window).

• CiRXFnEID: ECAN Acceptance Filter Extended Identifier Register n (n = 0-15)

These 16 registers specify the extended identifier (EID) for acceptance filters 0-15. The

identifier bits are selectively masked against the incoming message identifier to determine

if the message should be accepted or rejected (see Register 21-5). These registers are only

accessible by the user application when the WIN bit is set (CiCTRL1<0> = 1).

• CiRXMnSID: ECAN Acceptance Filter Mask Standard Identifier Register n (n = 0-2)

These three registers specify the SID mask bits for Acceptance Masks 0, 1 and 2. Any

acceptance filter can optionally select one of these mask registers to selectively compare

the identifier bits (see Register 21-6). These registers are only accessible by the user

application when the WIN bit is set (CiCTRL1<0> = 1).

• CiRXMnEID: ECAN Acceptance Filter Mask Extended Identifier Register n (n = 0-2)

There are three pairs of registers that specify Acceptance Mask bits for Mask 0, 1 and 2. Any

acceptance filter can optionally select one of the mask registers to selectively compare the

identifier bits (see Register 21-7). These registers are only accessible by the user

application when the WIN bit is set (CiCTRL1<0> = 1).

Note:

Each dsPIC33E/PIC24E family device variant may have one or more ECAN

modules. An ‘i’ used in the names of pins, control/status bits and registers denotes

the particular ECAN module number. Refer to the “Enhanced Controller Area

Network (ECAN™)” chapter in the specific device data sheet for the number of

available ECAN modules.

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