376 datasheet(40/95 Pages) INTEL

40 / 95 page

376 EMBEDDED PROCESSOR

240182 – 18

NOTE

Since A23 is HIGH during automatic communication with coprocessor A23 HIGH and MIO LOW can be used to easily

generate a coprocessor select signal

Figure 43 Physical Memory and IO Spaces

44 Bus Functional Description

The 80376 has separate parallel buses for data and

address The data bus is 16 bits in width and bidi-

rectional The address bus provides a 24-bit value

using 23 signals for the 23 upper-order address bits

and 2 Byte Enable signals to directly indicate the

active bytes These buses are interpreted and con-

trolled by several definition signals

The definition of each bus cycle is given by three

signals MIO WR and DC At the same time a

valid address is present on the byte enable signals

BHE and BLE

and the other address signals

A23–A1 A status signal ADS indicates when the

80376 issues a new bus cycle definition and ad-

dress

Collectively the address bus data bus and all asso-

ciated control signals are referred to simply as ‘‘the

bus’’ When active the bus performs one of the bus

cycles below

1 Read from memory space

2 Locked read from memory space

3 Write to memory space

4 Locked write to memory space

5 Read from IO space (or coprocessor)

6 Write to IO space (or coprocessor)

7 Interrupt acknowledge (always locked)

8 Indicate halt or indicate shutdown

Table 42 shows the encoding of the bus cycle defi-

nition signals for each bus cycle See Bus Cycle

Definition Signals

for additonal information

When the 80376 bus is not performing one of the

activities listed above it is either Idle or in the Hold

Acknowledge state which may be detected by ex-

ternal circuitry The idle state can be identified by the

80376 giving no further assertions on its address

strobe output (ADS) since the beginning of its most

recent bus cycle and the most recent bus cycle hav-

ing been terminated The hold acknowledge state is

identified by the 80376 asserting its hold acknowl-

edge (HLDA) output

The shortest time unit of bus activity is a bus state A

bus state is one processor clock period (two CLK2

periods) in duration A complete data transfer occurs

during a bus cycle composed of two or more bus

states

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