376 datasheet(37/95 Pages) INTEL

37 / 95 page

376 EMBEDDED PROCESSOR

Wait states affect HOLD latency The 80376 will not

honor a HOLD request until the end of the current

bus operation no matter how many wait states are

required Systems with DMA where data transfer is

critical must insure that READY returns sufficiently

soon

COPROCESSOR INTERFACE SIGNALS

(PEREQ BUSY ERROR)

In the following sections are descriptions of signals

dedicated to the numeric coprocessor interface In

addition to the data bus address bus and bus cycle

definition signals these following signals control

communication

between

the

80376

and

the

80387SX processor extension

Coprocessor Request (PEREQ)

When asserted (HIGH) this input signal indicates a

coprocessor request for a data operand to be trans-

ferred tofrom memory by the 80376 In response

the 80376 transfers information between the co-

processor and memory Because the 80376 has in-

ternally stored the coprocessor opcode being exe-

cuted it performs the requested data transfer with

the correct direction and memory address

PEREQ is a level-sensitive active HIGH asynchro-

nous signal Setup and hold times t29 and t30 rela-

tive to the CLK2 signal must be met to guarantee

recognition at a particular clock edge This signal is

provided with a weak internal pull-down resistor of

around 20 KX to ground so that it will not float active

when left unconnected

Coprocessor Busy (BUSY)

When asserted (LOW) this input indicates the co-

processor is still executing an instruction and is not

yet able to accept another When the 80376 en-

counters any coprocessor instruction which oper-

ates on the numerics stack (eg load pop or arith-

metic operation) or the WAIT instruction this input

is first automatically sampled until it is seen to be

inactive This sampling of the BUSY input prevents

overrunning the execution of a previous coprocessor

instruction

The F(N)INIT F(N)CLEX coprocessor instructions

are allowed to execute even if BUSY is active since

these instructions are used for coprocessor initializa-

tion and exception-clearing

BUSY is an active LOW level-sensitive asynchro-

nous signal Setup and hold times t29 and t30 rela-

tive to the CLK2 signal must be met to guarantee

recognition at a particular clock edge This pin is pro-

vided with a weak internal pull-up resistor of around

20 KX to VCC so that it will not float active when left

unconnected

BUSY serves an additional function If BUSY is sam-

pled LOW at the falling edge of RESET the 80376

processor performs an internal self-test (see Bus

Activity During and Following Reset

If BUSY is

sampled HIGH no self-test is performed

Coprocessor Error (ERROR)

When asserted (LOW) this input signal indicates

that the previous coprocessor instruction generated

a coprocessor error of a type not masked by the

coprocessor’s control register This input is automat-

ically sampled by the 80376 when a coprocessor

instruction is encountered and if active the 80376

generates exception 16 to access the error-handling

software

Several coprocessor instructions generally those

which clear the numeric error flags in the coproces-

sor or save coprocessor state do execute without

the

80376

generating

exception

even

ERROR is active These instructions are FNINIT

FNCLEX

FNSTSW

FNSTSWAX

FNSTCW

FNSTENV and FNSAVE

ERROR is an active LOW level-sensitive asynchro-

nous signal Setup and hold times t29 and t30 rela-

tive to the CLK2 signal must be met to guarantee

recognition at a particular clock edge This pin is pro-

vided with a weak internal pull-up resistor of around

20 KX to VCC so that it will not float active when left

unconnected

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