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376 датащи(PDF) 23 Page - Intel Corporation |
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376 датащи(HTML) 23 Page - Intel Corporation |
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23 / 95 page ![]() 376 EMBEDDED PROCESSOR SINGLE-STEP TRAP If the single-step flag (TF bit 8) in the EFLAG regis- ter is found to be set at the end of an instruction a single-step exception occurs The single-step ex- ception is auto vectored to exception number 1 The Debug Registers are an advanced debugging feature of the 80376 They allow data access break- points as well as code execution breakpoints Since the breakpoints are indicated by on-chip registers an instruction execution breakpoint can be placed in ROM code or in code shared by several tasks nei- ther of which can be supported by the INT 3 break- point opcode The 80376 contains six Debug Registers consisting of four breakpoint address registers and two break- point control registers Initially after reset break- points are in the disabled state therefore no break- points will occur unless the debug registers are programmed Breakpoints set up in the Debug Registers are auto-vectored to exception 1 Figure 26 shows the breakpoint status and control registers 30 ARCHITECTURE The Intel 80376 Embedded Processor has a physi- cal address space of 16 Mbytes (224 bytes) and al- lows the running of virtual memory programs of al- most unlimited size (16 Kbytes c 16 Mbytes or 256 Gbytes (238 bytes)) In addition the 80376 pro- vides a sophisticated memory management and a hardware-assisted protection mechanism 31 Addressing Mechanism The 80376 uses two components to form the logical address a 16-bit selector which determines the lin- ear base address of a segment and a 32-bit effec- tive address The selector is used to specify an index into an operating system defined table (see Figure 31) The table contains the 32-bit base ad- dress of a given segment The linear address is formed by adding the base address obtained from the table to the 32-bit effective address This value is truncated to 24 bits to form the physical address which is then placed on the address bus 240182 – 11 Figure 31 Address Calculation 23 |
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